Testing integrated circuits is expensive and time consuming. Complex very large scale integrated (VLSI) chips can have millions of internal nodes. Probing all of the nodes in the silicon during a debug process is difficult.
Existing solutions are inefficient, time consuming and expensive. Existing test methods include opening up a chip and using an electronic probing device. Opening up a chip can destroy the chip. Electronic probing tests one node at a time. The entire set up (i.e., chip, circuit board and system) can be too large to fit inside a vacuum chamber. Testing can require special infinite loop test patterns. However, the test patterns may not be able to reproduce the problem.
It would be desirable to implement a built-in logic to allow observation of internal nodes of a chip under normal operating conditions.